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Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators.

, , and . IEEE Micro, 37 (3): 12-21 (2017)

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Design analysis of a heterogeneous distributed system., and . ACM SIGOPS European Workshop, ACM, (1986)An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs., , and . ISPASS, page 116-118. IEEE, (2020)Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing., , , , , , , , , and 2 other author(s). ACM Trans. Comput. Syst., (2023)Unlocking Ordered Parallelism with the Swarm Architecture., , , , and . IEEE Micro, 36 (3): 105-117 (2016)Shared Resources for Multiple Instruction Stream Pipelined Processors. University of Illinois Urbana-Champaign, USA, (1979)Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators., , , , and . ISPASS, page 232-234. IEEE, (2021)Adaptive insertion policies for high performance caching., , , , and . ISCA, page 381-391. ACM, (2007)SpZip: Architectural Support for Effective Data Compression In Irregular Applications., , and . ISCA, page 1069-1082. IEEE, (2021)Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling., , , , , , , , , and 1 other author(s). ASPLOS (3), page 18-32. ACM, (2023)CRUISE: cache replacement and utility-aware scheduling., , , , and . ASPLOS, page 249-260. ACM, (2012)