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Disambiguation of "Sohn, Young-Soo"

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A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.

, , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)

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Soo-Young Kim

Young-Soo Chang

Young-Soo Han

Young-Taek Sohn

Hae-Young Sohn

 

Other publications of authors with the same name

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme., , , , , and . IEEE J. Solid State Circuits, 37 (2): 245-250 (2002)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond., , , , , , , , , and 10 other author(s). HCS, page 1-26. IEEE, (2021)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process., , , , , , , , , and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM., , , , , , , , , and 7 other author(s). A-SSCC, page 139-142. IEEE, (2018)A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel., , , , , , , and . CICC, page 1-4. IEEE, (2010)A 1-Gb/s bidirectional I/O buffer using the current-mode scheme., , , , and . IEEE J. Solid State Circuits, 34 (4): 529-535 (1999)Design and fabrication of a vibration sensor using a conductive ball., , , and . Microelectron. J., 38 (3): 416-421 (2007)A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1645-1656 (2009)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)