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The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors.

, , , , and . IEEE Trans. Computers, 44 (3): 353-370 (1995)

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Tolerating First Level Memory Access Latency in High-Performance Systems., , and . ICPP (1), page 36-43. CRC Press, (1992)The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs., , , , and . ICPP (2), page 142-145. CRC Press, (1991)Systematic Register Bypass Customization for Application-Specific Processors., , , , , , and . ASAP, page 64-74. IEEE Computer Society, (2003)StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs., , , and . IEEE Trans. Computers, 60 (1): 5-19 (2011)Embracing heterogeneity with dynamic core boosting., and . Conf. Computing Frontiers, page 10:1-10:10. ACM, (2014)Sentinel Scheduling for VLIW and Superscalar Processors., , , , , , and . ACM Trans. Comput. Syst., 11 (4): 376-408 (1993)preliminary version: ASPLOS 1992: 238-247.Input responsiveness: using canary inputs to dynamically steer approximation., , , , , and . PLDI, page 161-176. ACM, (2016)Sentinel Scheduling for VLIW and Superscalar Processors., , , , and . ASPLOS, page 238-247. ACM Press, (1992)long version: TOCS 11(4): 376-408.Reverse If-Conversion., , , and . PLDI, page 290-299. ACM, (1993)Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory., , , and . PLDI, page 166-176. ACM, (2009)