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Modeling of dynamic errors in algorithmic A/D converters., , and . ISCAS (5), page 455-458. IEEE, (2001)A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS., , , and . ISSCC, page 424-613. IEEE, (2007)Design and Analysis of a Class-D Stage With Harmonic Suppression., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (6): 1178-1186 (2012)Application of Knowledge-based System in a B-to-B Environment., , and . IMSA, page 152-157. IASTED/ACTA Press, (2002)Envelope detector sensitivity and blocking characteristics., and . ECCTD, page 773-776. IEEE, (2011)Bitline leakage equalization for sub-100nm caches., , , , , and . ESSCIRC, page 401-404. IEEE, (2003)A low-swing single-ended L1 cache bus technique for sub-90nm technologies., , , , and . ESSCIRC, page 475-477. IEEE, (2004)A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS., , and . ESSCIRC, page 310-313. IEEE, (2010)Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits., , and . ISLPED, page 245-249. ACM, (1998)GLMC: interconnect length estimation by growth-limited multifold clustering., , and . ISCAS, page 465-468. IEEE, (2000)