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Disambiguation of "Huang, Chung-Hsun"

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ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs.

, , , , , and . ASICON, page 47-50. IEEE, (2011)

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Yu-chung Huang

Chien-Chung Huang

Chung-cheng Huang

Hsun Shan Chen

Hsun-Yang Chang

 

Other publications of authors with the same name

A high-speed CMOS incrementer/decrementer., , and . ISCAS (4), page 88-91. IEEE, (2001)A fast wake-up power gating technique with inducing a balanced rush current., , , and . ISCAS, page 3086-3089. IEEE, (2012)A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches., and . IEEE Trans. Very Large Scale Integr. Syst., 28 (5): 1141-1149 (2020)Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET)., , , , , , , , , and . Hot Chips Symposium, page 1. IEEE, (2014)Design and Implementation of Machine Tool Life Inspection System Based on Sound Sensing., , , , , and . Sensors, 23 (1): 284 (2023)A low-voltage high PSR LDO regulator with a simple ripple cancellation technique., , and . IEICE Electron. Express, 11 (20): 20140906 (2014)A compact programmable LDO regulator for ultra-low voltage SoC., and . IEICE Electron. Express, 11 (20): 20140820 (2014)The CMOS carry-forward adders., , , and . IEEE J. Solid State Circuits, 39 (2): 327-336 (2004)Towards Efficient Neural Network on Edge Devices via Statistical Weight Pruning., , , and . GCCE, page 192-193. IEEE, (2020)Adaptive Pseudo Dual Keeper for Wide Fan-In Dynamic Circuits., , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (10): 672-676 (2011)