Author of the publication

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.

, , , , , , , and . ICICDT, page 1-4. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit., , , , , , , , , and 1 other author(s). ISSCC, page 320-321. IEEE, (2013)A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs., , , , , , , and . VLSIC, page 100-101. IEEE, (2012)A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver., , , , , , , , , and 3 other author(s). ISSCC, page 458-459. IEEE, (2009)Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation., , , , , , and . ITC, page 1-7. IEEE Computer Society, (2008)DFT techniques for memory macro with built-in ECC., , , and . MTDT, page 109-114. IEEE Computer Society, (2005)Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction., , , , , , , and . ICICDT, page 1-4. IEEE, (2012)A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 49 (1): 118-126 (2014)A low leakage SRAM macro with replica cell biasing scheme., , , , and . IEEE J. Solid State Circuits, 41 (4): 815-822 (2006)13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current., , , , , , , , and . ISSCC, page 236-237. IEEE, (2014)A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell., , , , , , , , , and 1 other author(s). ISSCC, page 382-383. IEEE, (2008)