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Automated Design Error Localization in RTL Designs., , , , , , , , and . IEEE Des. Test, 31 (1): 83-92 (2014)Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation., , , , , , and . EvoApplications, volume 8602 of Lecture Notes in Computer Science, page 425-436. Springer, (2014)Evaluating Fault Emulation on FPGA., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 354-363. Springer, (2004)Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs., , , , , , and . ATS, page 304-309. IEEE Computer Society, (2016)Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits., , , , , , , , , and 2 other author(s). J. Electron. Test., 32 (3): 273-289 (2016)A scalable model based RTL framework zamiaCAD for static analysis., , , , , and . VLSI-SoC, page 171-176. IEEE, (2012)Localization of Bugs in Processor Designs Using zamiaCAD Framework., , , , , , and . MTV, page 41-47. IEEE Computer Society, (2012)Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG., , , , , , , , , and 1 other author(s). LATS, page 1-6. IEEE Computer Society, (2015)PSL assertion checkers synthesis with ASM based HLS tool ABELITE., , , and . LATW, page 1-6. IEEE Computer Society, (2012)Assessment of diagnostic test for automated bug localization., , , , and . LATW, page 1-6. IEEE Computer Society, (2013)