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Corrigendum to "High throughput asynchronous NoC design under high process variation" Integr. VLSI J. (2015) 1-13., , and . Integr., (2016)Optimum wire sizing of RLC interconnect with repeaters ., and . Integr., 38 (2): 205-225 (2004)Wire shaping of RLC interconnects., and . Integr., 40 (4): 461-472 (2007)Asynchronous BFT for low power networks on chip., , , and . ISCAS, page 3240-3243. IEEE, (2010)Low-Power NoC Using Optimum Adaptation., , , and . Computational Intelligence in Digital and Network Designs and Applications, Springer, (2015)Efficient embedded SoC hardware/software codesign using virtual platform., , , and . IDT, page 36-38. IEEE, (2014)High performance interpolation filter using direct computation., , , , , and . IDT, page 121-124. IEEE, (2016)High throughput asynchronous NoC switch for high process variation., , and . IDT, page 1-4. IEEE, (2013)Inductive interconnect width optimization for low power., and . ISCAS (5), page 273-276. IEEE, (2003)Brain-in-Car: A Brain Activity-based Emotion Recognition Embedded System for Automotive., , , , , , , , , and . ICVES, page 1-5. IEEE, (2019)