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High Speed FPGA-Based Implementations of Delayed-LMS Filters., , , and . VLSI Signal Processing, 39 (1-2): 113-131 (2005)Multidimensional DSP Core Synthesis for FPGA., , , and . VLSI Signal Processing, 43 (2-3): 207-221 (2006)On the Key Generation From Correlated Wireless Channels., , , and . IEEE Communications Letters, 21 (4): 961-964 (2017)Optimized bit level architectures for IIR filtering., , and . ICCD, page 302-306. IEEE Computer Society, (1990)Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations., , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 551-563. Springer, (2018)FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG., , , , , and . ARC, volume 9625 of Lecture Notes in Computer Science, page 78-90. Springer, (2016)Memory-Centric Hardware Synthesis from Dataflow Models., , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 197-206. Springer, (2008)Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems., , and . FPL, page 447-448. IEEE Computer Society, (2018)Soft IP core implementation of recursive least squares filter using only multplicative and additive operators., , and . FPL, page 597-600. IEEE, (2007)How Resistant are Sboxes to Power Analysis Attacks?, , and . NTMS, page 1-6. IEEE, (2011)