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Achieving Exascale Capabilities through Heterogeneous Computing., , , , , , , , , and . IEEE Micro, 35 (4): 26-36 (2015)Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap., and . IEEE Micro, 32 (3): 70-78 (2012)Width-Partitioned Load Value Predictors.. J. Instruction-Level Parallelism, (2003)Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors., , and . J. Instruction-Level Parallelism, (2003)Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors., and . DAC, page 622-625. IEEE, (2007)There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes., , , , , and . ISCA, page 678-690. ACM, (2017)Energy-efficient GPU design with reconfigurable in-package graphics memory., , , and . ISLPED, page 403-408. ACM, (2012)PEEP: Exploiting predictability of memory dependences in SMT processors., , and . HPCA, page 137-148. IEEE Computer Society, (2008)Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems., , , and . MEMSYS, page 3-10. ACM, (2015)A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches., , , and . IEEE Micro, 34 (3): 80-90 (2014)