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Disambiguation of "Ravi, Ashoke"

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A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.

, , , , , , and . IEEE J. Solid State Circuits, 45 (7): 1410-1420 (2010)

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Ravi Walli

Mylapore Ravi

Holger Raviol

Jewgeni Ravik

Fausto Ravida

 

Other publications of authors with the same name

A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS., , , , , and . ISSCC, page 70-72. IEEE, (2012)A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 168-170. IEEE, (2012)8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS., , , and . CICC, page 625-628. IEEE, (2004)A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement., , , , , , and . IEEE J. Solid State Circuits, 47 (7): 1646-1658 (2012)A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O., , , , and . ISLPED, page 1-6. IEEE, (2017)A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost., , , , , , , , , and . ISSCC, page 186-187. IEEE, (2023)A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 451-453. IEEE, (2021)A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving., , , , , , and . ESSCIRC, page 152-155. IEEE, (2009)A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 51 (12): 2992-3004 (2016)A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique., , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1721-1729 (2013)