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Disambiguation of "Choi, Young-Kyoung"

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Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.

, , , , , , , , , , , , and . ISSCC, page 280-281. IEEE, (2008)

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Jin Kyoung Choi

Kyoung Moo Choi

Young-Soon Choi

Se-Young Choi

Jin-Young Choi

 

Other publications of authors with the same name

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface., , , , , , , , , and 3 other author(s). ISSCC, page 280-281. IEEE, (2008)A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology., , , , , , , , , and 12 other author(s). ISSCC, page 282-283. IEEE, (2008)A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 131-140 (2012)A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology., , , , , , , , and . ISSCC, page 502-504. IEEE, (2011)A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL., , , , , , , , , and 3 other author(s). ISSCC, page 547-556. IEEE, (2006)