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Disambiguation of "Fukazawa, Mitsuya"

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Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.

, , , , , , and . CICC, page 35-38. IEEE, (2005)

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Naritaka Fukazawa

 

Other publications of authors with the same name

A built-in power supply noise probe for digital LSIs., , , and . ASP-DAC, page 106-107. IEEE, (2006)Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations., , , , and . IEICE Trans. Electron., 92-C (4): 475-482 (2009)A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction., , , , , , and . IEEE J. Solid State Circuits, 56 (10): 2943-2955 (2021)A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer., and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs., , , , , , , and . ISSCC, page 288-603. IEEE, (2007)Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform., and . CICC, page 865-868. IEEE, (2006)Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise., and . IEICE Trans. Electron., 89-C (11): 1559-1566 (2006)A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing Applications., , , , , , , , , and 2 other author(s). A-SSCC, page 1-4. IEEE, (2020)9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS., , , , , , , and . ISSCC, page 166-168. IEEE, (2020)Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias., , , , , , and . CICC, page 35-38. IEEE, (2005)