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Disambiguation of "Lakdawala, Hasnain"

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A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control.

, , , , , , and . ESSCIRC, page 131-134. IEEE, (2011)

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Zahra Lakdawala

Hasnain Raza

Chang-Hasnain

Hasnain Ghazi

Syed Nazrul Hasnain

 

Other publications of authors with the same name

A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS., , , , and . ISSCC, page 426-428. IEEE, (2011)32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver., , , , , , , , , and 13 other author(s). ISSCC, page 62-64. IEEE, (2012)A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction., , , , , , , and . CICC, page 813-816. IEEE, (2005)A 0.5 mm2 integrated capacitive vibration sensor with sub-10 zF/rt-Hz noise floor., , , , , , , and . CICC, page 93-96. IEEE, (2005)A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 44 (6): 1668-1678 (2009)A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver., , , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1669-1679 (2013)A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS., , , , , , , , , and 5 other author(s). VLSIC, page 76-77. IEEE, (2012)A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS., , , , and . CICC, page 1-4. IEEE, (2009)Analog techniques II., and . CICC, page 1. IEEE, (2013)A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 48 (1): 91-103 (2013)