( en | de | ru )

 

Disambiguation of "Saxena, Nirmal R."

Author of the publication

copydeleteadd this publication to your clipboard
Floating Point Fault Tolerance with Backward Error Assertions.

, , , , and . IEEE Trans. Computers, 44 (2): 302-311 (1995)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Abhinav Saxena

Ambrish Saxena

Amit Saxena

Sabine Saxena

Krishna Saxena

 

Other publications of authors with the same name

A Unified View of Test Compression Methods., and . IEEE Trans. Computers, 36 (1): 94-99 (1987)Counting Two-State Transition-Tour Sequences., and . IEEE Trans. Computers, 45 (11): 1337-1342 (1996)Floating Point Fault Tolerance with Backward Error Assertions., , , , and . IEEE Trans. Computers, 44 (2): 302-311 (1995)Characterizing and Mitigating Soft Errors in GPU DRAM., , , , , , , , and . MICRO, page 641-653. ACM, (2021)Techniques for Estimation of Design Diversity for Combinational Logic Circuits., , and . DSN, page 25-36. IEEE Computer Society, (2001)Low Overhead Tag Error Mitigation for GPU Architectures., , , , and . DSN, page 314-321. IEEE Computer Society, (2018)Design Verification of a Super-Scalar RISC Processor., , , , , , , and . FTCS, page 472-477. IEEE Computer Society, (1995)On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors., , , , and . ITC, page 1-10. IEEE, (2020)Error Model (EM) - A New Way of Doing Fault Simulation., and . ITC, page 324-333. IEEE, (2022)Finite state machine synthesis with concurrent error detection., , and . ITC, page 672-679. IEEE Computer Society, (1999)