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Registers for Phase Difference Based Logic., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (6): 720-724 (2007)Significance-Driven Logic Compression for Energy-Efficient Multiplier Design., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)Step Persistence in the Design of GALS Systems., , , , and . Petri Nets, volume 7927 of Lecture Notes in Computer Science, page 190-209. Springer, (2013)Design and Implementation of Reconfigurable Asynchronous Pipelines., , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1527-1539 (2020)Towards power-elastic systems through concurrency management., , , , , , , and . IET Comput. Digit. Tech., 6 (1): 33-42 (2012)An Excitation Time Model for General-purpose Memristance Tuning Circuit., , , and . ISCAS, page 1-5. IEEE, (2018)Automating the Design of Asynchronous Logic Control for AMS Electronics., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (5): 952-965 (2020)Direct Mapping of Low-Latency Asynchronous Controllers From STGs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (6): 993-1009 (2007)Online Testing by Protocol Decomposition., , , and . IOLTS, page 263-268. IEEE Computer Society, (2006)Toward Designing Thermally-Aware Memristance Decoder., , , , and . ISCAS, page 1. IEEE, (2020)