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Loop Optimization in Register-Transfer Scheduling for DSP-Systems.

, , and . DAC, page 826-831. ACM Press, (1989)

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An integrated automatic design system for complex DSP algorithms., , , , , , , , , and . VLSI Signal Processing, 1 (4): 265-278 (1990)Models for bit-true simulation and high-level synthesis of DSP applications., , , , and . Great Lakes Symposium on VLSI, page 52-59. IEEE, (1992)A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report., , , , , , , , , and 2 other author(s). CoRR, (2013)Real-time multi-tasking in software synthesis for information processing systems., , , and . ISSS, page 48-53. ACM, (1995)Open-ended system for high-level synthesis of flexible signal processors., , , , , and . EURO-DAC, page 272-276. IEEE Computer Society, (1990)A generalized state assignment theory for transformation on signal transition graphs., , , and . ICCAD, page 112-117. IEEE Computer Society / ACM, (1992)Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures., , , and . VLSI Signal Processing, 11 (1-2): 97-112 (1995)An efficient microcode compiler for application specific DSP processors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (9): 925-937 (1990)Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications., , , and . ICCAD, page 184-187. IEEE Computer Society, (1990)Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization., , , and . EDAC-ETC-EUROASIC, page 490-494. IEEE Computer Society, (1994)