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Disambiguation of "Pleskacz, Witold A."

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A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (2): 151-162 (1999)

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Witold Jeszke

Witold Lesniak

Witold Ostapowicz

Witold Zenk

Witold Slowinski

 

Other publications of authors with the same name

A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (2): 151-162 (1999)Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement., , , , , and . Microelectron. Reliab., 41 (12): 2023-2040 (2001)Hierarchical test generation for combinational circuits with real defects coverage., , , , , , and . Microelectron. Reliab., 42 (7): 1141-1149 (2002)IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology., , and . MIXDES, page 334-338. IEEE, (2015)Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology., , , and . DDECS, page 259-262. IEEE Computer Society, (2008)LC-VCO design automation tool for nanometer CMOS technology., , and . DDECS, page 68-73. IEEE, (2012)PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications., , and . DDECS, page 29-34. IEEE Computer Society, (2011)Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS., , and . DDECS, page 78-83. IEEE Computer Society, (2009)Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC., , , , , and . DSD, page 729-734. IEEE Computer Society, (2008)Yield Estimation of VLSI Circuits with Downscaled Layouts.. DFT, page 55-60. IEEE Computer Society, (1999)