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Disambiguation of "Calazans, Ney Laert Vilar"

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Design and analysis of the HF-RISC processor targeting voltage scaling applications.

, , , , , , and . SBCCI, page 1-6. IEEE, (2016)

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Loreto Vilar

Ignazio Vilardi

Fabio Vilardi

Sisi Alexandra Vilardi

David Vilar Torres

 

Other publications of authors with the same name

Evaluating the scalability of test buses., , , , , and . ISSoC, page 1-6. IEEE, (2013)A processor for IoT applications: An assessment of design space and trade-offs., , , , and . Microprocess. Microsystems, (2016)A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits., , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (2): 15:1-15:23 (2016)Static Differential NCL Gates: Toward Low Power., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (6): 563-567 (2015)Leveraging QDI Robustness to Simplify the Design of IoT Circuits., , , , and . ISCAS, page 1-5. IEEE, (2020)Requirements, Primitives and Models for Systems Specification., , and . SBCCI, page 323-330. IEEE Computer Society, (2002)Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits., , , , , and . VLSID, page 321-326. IEEE Computer Society, (2015)A generic FPGA emulation framework., , , , , , , and . ICECS, page 233-236. IEEE, (2012)XGT4: An industrial grade, open source tester for multi-gigabit networks., , , , and . ICECS, page 252-255. IEEE, (2017)A path towards average-case silicon via asynchronous resilient bundled-data design., and . ECCTD, page 1-4. IEEE, (2015)