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PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.

, , , , , , , and . ISCA, page 27-39. IEEE Computer Society, (2016)

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In-memory multiplication engine with SOT-MRAM based stochastic computing., , , , , and . CoRR, (2018)NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs., , , , , and . ACM Trans. Archit. Code Optim., 17 (4): 31:1-31:25 (2020)NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting., , , , and . ICCAD, page 28:1-28:9. IEEE, (2020)Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network., , , , , , , , , and 4 other author(s). ISCA, page 946-961. ACM, (2022)AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip., , , , , , , , and . ASP-DAC, page 146-151. ACM, (2019)Architecture exploration for ambient energy harvesting nonvolatile processors., , , , , , , , and . HPCA, page 526-537. IEEE Computer Society, (2015)CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators., , , , and . ACM Great Lakes Symposium on VLSI, page 283-286. ACM, (2019)SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator., , , , , , , , and . MICRO, page 696-709. IEEE Computer Society, (2018)Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators., , , , , , , , , and 1 other author(s). ISLPED, page 1-6. IEEE, (2019)Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 55 (8): 2228-2246 (2020)