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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal, and M. Valero. ISLPED, page 362-367. ACM, (2016)

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Oscar Romero

Oscar Jacob

Oscar Lücke

Oscar Zaepke

Oscar Meckel

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PETS: Power and energy estimation tool at system-level.S. Rethinagiri, O. Palomar, O. Unsal, A. Cristal, R. Atitallah, and S. Niar. ISQED, page 535-542. IEEE, (2014)Dynamic-vector execution on a general purpose EDGE chip multiprocessor.M. Duric, O. Palomar, A. Smith, M. Stanic, O. Unsal, A. Cristal, M. Valero, D. Burger, and A. Veidenbaum. ICSAMOS, page 18-25. IEEE, (2014)Power estimation tool for system on programmable chip based platforms (abstract only).S. Rethinagiri, O. Palomar, A. Cristal, and O. Unsal. FPGA, page 256. ACM, (2014)A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures.C. Ramírez, C. Hernández-Calderón, O. Palomar, O. Unsal, M. Ramírez, and A. Cristal. ACM Trans. Archit. Code Optim., 17 (4): 38:1-38:30 (2020)DVINO: A RISC-V Vector Processor Implemented in 65nm Technology.G. Cabo, G. Candón, X. Carril, M. Doblas, M. Domínguez, A. González, C. Hernández, V. Jiménez, V. Kostalampros, R. Langarita and 33 other author(s). DCIS, page 1-6. IEEE, (2022)POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core.M. Stanic, O. Palomar, T. Hayes, I. Ratkovic, O. Unsal, A. Cristal, and M. Valero. PACT, page 447-448. ACM, (2016)Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020).M. Pericàs, O. Palomar, V. Papaefstathiou, and M. Eljammaly. CoRR, (2020)ViPS: Visual processing system for medical imaging.T. Hussain, O. Palomar, A. Cristal, E. Ayguadé, and A. Haider. BMEI, page 40-45. IEEE, (2015)Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi.M. Stanic, O. Palomar, I. Ratkovic, M. Duric, O. Unsal, A. Cristal, and M. Valero. HPCS, page 47-54. IEEE, (2014)Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal, and M. Valero. IEEE Trans. Very Large Scale Integr. Syst., 26 (4): 639-652 (2018)

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Disambiguation of "Palomar, Oscar"

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A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

Please choose a person to relate this publication to

Oscar Romero

Oscar Jacob

Oscar Lücke

Oscar Zaepke

Oscar Meckel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Palomar, Oscar"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

Please choose a person to relate this publication to

Oscar Romero

Oscar Jacob

Oscar Lücke

Oscar Zaepke

Oscar Meckel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.