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Disambiguation of "Tokairin, Takashi"

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A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy.

, , , , , , , , , and . A-SSCC, page 1-4. IEEE, (2016)

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Takashi Seki

Takashi Iwata

Takashi Tsuno

Takashi Numaguchi

Takashi Ohtsuki

 

Other publications of authors with the same name

A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX., , , , , , and . ESSCIRC, page 314-317. IEEE, (2018)A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme., , , , , , and . VLSIC, page 16-17. IEEE, (2012)A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC., , , , and . ISSCC, page 470-471. IEEE, (2010)A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy., , , , , , , , , and . A-SSCC, page 1-4. IEEE, (2016)A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter., , , , and . IEEE J. Solid State Circuits, 45 (12): 2582-2590 (2010)A 3.2mA-RX 3.5mA-TX Fully Integrated SoC for Bluetooth Low Energy System., , , , , , , , , and . IEICE Trans. Electron., 100-C (10): 833-840 (2017)Analytical Expression of Quantization Noise in Time-to-Digital Converter Based on the Fourier Series Analysis., and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (7): 1538-1548 (2010)A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme., , , and . IEEE J. Solid State Circuits, 46 (3): 572-582 (2011)A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 51 (12): 3125-3136 (2016)An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX., , , , , , , , , and . VLSI Circuits, page 25-26. IEEE, (2018)