( en | de | ru )

 

Disambiguation of "Matsuzawa, Akira"

Author of the publication

copydeleteadd this publication to your clipboard
A time-domain architecture and design method of high speed A-to-D converters with standard cells.

, , , , and . A-SSCC, page 353-356. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Akira Hayashima

Akira Hori

Akira Satake

Akira Hayashima

Akira Yasui

 

Other publications of authors with the same name

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator., , , , , and . IEEE J. Solid State Circuits, 45 (4): 697-706 (2010)A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration., , , , , and . IEEE J. Solid State Circuits, 49 (1): 50-60 (2014)A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC., , , and . IEEE J. Solid State Circuits, 51 (10): 2345-2356 (2016)Feedforward compensation technique for all digital phase locked loop based synthesizers., , and . ISCAS, IEEE, (2006)A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 422-433 (2013)A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition., , and . IEICE Trans. Electron., 95-C (7): 1285-1296 (2012)A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells., , , and . IEICE Trans. Electron., 101-C (4): 197-205 (2018)A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs., , and . IEICE Trans. Electron., 96-C (4): 577-585 (2013)Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design., , , , , and . IEICE Trans. Electron., 98-C (1): 35-44 (2015)Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (8): 1518-1527 (2015)