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Disambiguation of "Maulik, Prabir C."

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A 150MHz-400MHz DLL-Based Programmable Clock Multiplier with -7OdBc Reference Spur in 0.18um CMOS.

, and . CICC, page 757-760. IEEE, (2006)

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Prabir Dutt

Prabir Kumar Banerjee

Guido C C Clinckspoor

Thomas C C Knöbig

Ullrich C C Jagstaidt

 

Other publications of authors with the same name

A 16-bit 250-kHz delta-sigma modulator and decimation filter., , , and . IEEE J. Solid State Circuits, 35 (4): 458-467 (2000)Automating Analog Circuit Design using Constrained Optimization Techniques., and . ICCAD, page 390-393. IEEE Computer Society, (1991)A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis., , and . DAC, page 698-703. IEEE Computer Society Press, (1992)A 150MHz-400MHz DLL-Based Programmable Clock Multiplier with -7OdBc Reference Spur in 0.18um CMOS., and . CICC, page 757-760. IEEE, (2006)An analog/digital interface for cellular telephony., , , and . IEEE J. Solid State Circuits, 30 (3): 201-209 (March 1995)Frequency Tuning of Wide Temperature Range CMOS LC VCOs., and . IEEE J. Solid State Circuits, 46 (9): 2033-2040 (2011)A 12-bit integrated analog front-end for broadband wireline networks., , and . CICC, page 119-122. IEEE, (2001)Applications and Algorithm Partitioning on Warp., , , , , , , and . COMPCON, page 272-279. IEEE Computer Society, (1987)Comments on "FPAD: a fuzzy nonlinear programming approach to analog circuit design".. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (6): 656 (1997)A DLL-Based Programmable Clock Multiplier in 0.18-µm CMOS With -70 dBc Reference Spur., and . IEEE J. Solid State Circuits, 42 (8): 1642-1648 (2007)