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A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)

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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor., , , , , , , , , and 5 other author(s). ISSCC, page 98-99. IEEE, (2014)Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS., , , , and . CICC, page 1-4. IEEE, (2019)The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access., , , , , , , , , and 4 other author(s). ISSCC, page 1-3. IEEE, (2015)Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS., , , , and . IEEE J. Solid State Circuits, 55 (3): 731-743 (2020)A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI., , , , and . CICC, page 431-434. IEEE, (2008)A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)