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A reconfigurable cache architecture for energy efficiency., , and . Conf. Computing Frontiers, page 9. ACM, (2011)Energy Efficient And Low Latency Interconnection Network For Multicast Invalidates In Shared Memory Systems., , , and . AISTECS@HiPEAC, page 1:1-1:6. ACM, (2016)The HELIX project: overview and directions., , , , and . DAC, page 277-282. ACM, (2012)Helix: Making the Extraction of Thread-Level Parallelism Mainstream., , , , and . IEEE Micro, 32 (4): 8-18 (2012)Towards zero latency photonic switching in shared memory networks., , , and . Concurr. Comput. Pract. Exp., 26 (15): 2551-2566 (2014)HALO: post-link heap-layout optimisation., and . CGO, page 94-106. ACM, (2020)Performance implications of transient loop-carried data dependences in automatically parallelized loops., , , and . CC, page 23-33. ACM, (2016)The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation., , and . Int. J. Parallel Program., 41 (2): 305-330 (2013)On Verifying Timed Hyperproperties., , and . TIME, volume 147 of LIPIcs, page 20:1-20:18. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2019)Vector Runahead for Indirect Memory Accesses., , , and . IEEE Micro, 42 (4): 116-123 (2022)