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Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (8): 1265-1273 (2017)

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ORION 2.0: A Power-Area Simulator for Interconnection Networks., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 191-196 (2012)Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (6): 992-1003 (2017)CMP Fill Synthesis., and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks., , , , , and . CoRR, (2018)Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic., , , , , , , and . CoRR, (2019)Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology., , , , and . DATE, page 842-847. IEEE, (2019)BEOL stack-aware routability prediction from placement using data mining techniques., , , , and . ICCD, page 41-48. IEEE Computer Society, (2016)Improved on-chip router analytical power and area modeling., , and . ASP-DAC, page 241-246. IEEE, (2010)GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks., , , and . ISCA, page 650-661. IEEE Computer Society, (2018)SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks., , , , and . ISCA, page 662-673. IEEE Computer Society, (2018)