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An Efficient Contact Screening Method and its Application to High-Reliability Non-Volatile Memories.

, and . J. Electron. Test., 32 (4): 447-458 (2016)

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Design Methodology of an On-Chip Inductor in 180 nm CMOS Technology., , , and . MIPRO, page 65-69. IEEE, (2019)Variation and failure characterization through pattern classification of test data from multiple test stages., , , , , , and . ITC, page 1-10. IEEE, (2016)Design of CMOS Temperature Sensors Based on Ring Oscillators in 180-nm and 110-nm technology., , , and . MIPRO, page 104-108. IEEE, (2020)High efficient low cost EEPROM screening method in combination with an area optimized byte replacement strategy which enables high reliability EEPROMs., , , and . VTS, page 1-6. IEEE Computer Society, (2018)A 1-MHz Relaxation Oscillator Core Employing a Self-Compensating Chopped Comparator Pair., , and . ISCAS, page 1-4. IEEE, (2018)Automotive EEPROM Qualification and Cost Optimization., , and . Asian Test Symposium, page 105-106. IEEE Computer Society, (2013)Design of Sense Amplifiers for Non-Volatile Memory., , , and . MIPRO, page 59-64. IEEE, (2019)Temperature calibration of an on-chip relaxation oscillator., , , , and . MIPRO, page 93-97. IEEE, (2017)Semi-Analytical Estimation of On-Chip Intertwined Rectangular Transformer Parameters in 180 nm CMOS Technology., , , and . MIPRO, page 71-76. IEEE, (2020)Fault-based test methodology for analog amplifier circuits., , , and . EWDTS, page 1-7. IEEE Computer Society, (2017)