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2.5-dimensional VLSI system integration.

, and . IEEE Trans. Very Large Scale Integr. Syst., 13 (6): 668-677 (2005)

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Estimation of reject ratio in testing of combinatorial circuits., , , and . VTS, page 319-325. IEEE Computer Society, (1993)2.5-dimensional VLSI system integration., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (6): 668-677 (2005)Computer-aided failure analysis of VLSI circuits using IDDQ testing., and . VTS, page 106-108. IEEE Computer Society, (1993)Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 869-878 (2015)Can Defect-Tolerant Chips Better Meet the Quality Challenge?, , , , , and . VTS, page 362-363. IEEE Computer Society, (1996)Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (4): 495-506 (2014)