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Disambiguation of "Spessot, Alessio"

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Assessment of SiGe quantum well transistors for DRAM peripheral applications.

, , , , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

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Alessio Langiu

Alessio Meneghetti

Alessio Guerri

Alessio Vascon

Alessio Quaglino

 

Other publications of authors with the same name

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery., , , , , , , , , and 7 other author(s). IRPS, page 1-6. IEEE, (2022)Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations., , , , , , , , , and 1 other author(s). IMW, page 1-4. IEEE, (2022)Impact of Off State Stress on advanced high-K metal gate NMOSFETs., , , , , , and . ESSDERC, page 365-368. IEEE, (2014)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices., , , , , , , , , and 6 other author(s). IRPS, page 1-8. IEEE, (2019)Dedicated technology threshold voltage tuning for 6T SRAM beyond N7., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2017)I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration., , , , , , , , , and 2 other author(s). ICICDT, page 1-4. IEEE, (2015)SRAM designs for 5nm node and beyond: Opportunities and challenges., , , , , and . ICICDT, page 1-4. IEEE, (2017)Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm., , , , , and . IRPS, page 1-7. IEEE, (2021)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , and 2 other author(s). DAC, page 13. ACM, (2019)