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BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning.

, , , , , and . ITC, page 1-10. IEEE, (2016)

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Some considerations on choosing an outlier method for automotive product lines., , , , , and . ITC, page 1-10. IEEE, (2017)Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (8): 1405-1418 (2012)SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (5): 842-854 (2017)On-chip sensor selection for effective speed-binning., , , and . MWSCAS, page 1073-1076. IEEE, (2014)Forward prediction based on wafer sort data - A case study., , , , and . ITC, page 1-10. IEEE Computer Society, (2011)Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests., , and . VTS, page 1-6. IEEE Computer Society, (2014)Generalization of an outlier model into a "global" perspective., , , , , and . ITC, page 1-10. IEEE, (2015)Special session: Hot topic: Smart silicon., and . VTS, page 323. IEEE Computer Society, (2011)Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (9): 2602-2615 (2017)Fault-based Built-in Self-test and Evaluation of Phase Locked Loops., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 26 (3): 20:1-20:18 (2021)