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ULYSSES - a knowledge-based VLSI design environment., and . Artif. Intell. Eng., 2 (1): 33-41 (1987)Neural Net and Boolean Satisfiability Models of Logic Circuits., , , and . IEEE Des. Test Comput., 7 (5): 54-57 (1990)VLSI CAD tool integration using the Ulysses environment., and . DAC, page 55-61. IEEE Computer Society Press, (1986)MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing., and . DAC, page 107-110. IEEE Computer Society Press, (1990)Automatic Test Generation Using Quadratic 0-1 Programming., , and . DAC, page 654-659. IEEE Computer Society Press, (1990)Delay Fault Models and Test Generation for Random Logic Sequential Circuits., , and . DAC, page 165-172. IEEE Computer Society Press, (1992)Fault coverage estimation by test vector sampling., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (5): 590-596 (1995)Automated design tool execution in the Ulysses design environment., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (3): 279-287 (1989)The path-status graph with application to delay fault simulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (4): 324-332 (1998)Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework., , , and . EDAC-ETC-EUROASIC, page 610-617. IEEE Computer Society, (1994)