Author of the publication

Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level.

, , and . SBAC-PAD, page 222-229. IEEE Computer Society, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions., , , , , and . Int. J. Parallel Program., 49 (2): 237-252 (2021)Efficient Machine Learning execution with Near-Data Processing., , , , , and . Microprocess. Microsystems, (April 2022)Database Processing-in-Memory: An Experimental Study., , and . Proc. VLDB Endow., 13 (3): 334-347 (2019)SAPIVe: Simple AVX to PIM Vectorizer., , , and . SBESC, page 1-8. IEEE, (2022)Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors., , , , , , and . HPCC, page 491-496. IEEE, (2010)Operand size reconfiguration for big data processing in memory., , , , , and . DATE, page 710-715. IEEE, (2017)Introducing Drowsy Technique to Cache Line Usage Predictors., , and . WSCAD, page 259-265. IEEE, (2018)Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency., , , , and . PDP, page 388-392. IEEE Computer Society, (2016)TLP and ILP exploitation through a reconfigurable multiprocessor system., , , , , , , and . IPDPS Workshops, page 1-8. IEEE, (2010)Evaluating Dead Line Predictors Efficiency with Drowsy Technique., , and . SBESC, page 250-255. IEEE, (2018)