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Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 204-213 (2015)

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7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip., , , , , , , , , and 20 other author(s). ISSCC, page 1-3. IEEE, (2015)11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory., , , , , , , , , and 34 other author(s). ISSCC, page 202-203. IEEE, (2017)A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology., , , , , , , , , and 27 other author(s). ISSCC, page 430-432. IEEE, (2012)A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory., , , , , , , , , and 7 other author(s). VLSIC, page 132-133. IEEE, (2012)7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate., , , , , , , , , and 24 other author(s). ISSCC, page 1-3. IEEE, (2015)A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking., , , , , , , , , and 13 other author(s). ISSCC, page 496-498. IEEE, (2011)Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 204-213 (2015)1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture., , , , , , , , , and 5 other author(s). ISSCC, page 128-129. IEEE, (2009)A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity., , , , , , , , , and . IEEE J. Solid State Circuits, 36 (5): 735-743 (2001)A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 53 (1): 124-133 (2018)