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Test Considerations about the Structured ASIC Paradigm., and . DDECS, page 232-233. IEEE Computer Society, (2006)A novel scalable and reconfigurable emulation platform for embedded systems verification., , , , , and . ISCAS, page 865-868. IEEE, (2010)On the test of single via related defects in digital VLSI designs., , and . DDECS, page 1-6. IEEE, (2020)Recent Trends and Perspectives on Defect-Oriented Testing., , , , , , , , , and 11 other author(s). IOLTS, page 1-10. IEEE, (2022)Comparing different solutions for testing resistive defects in low-power SRAMs., , , , , , and . LATS, page 1-6. IEEE, (2021)Functional test generation for DMA controllers., , , , , and . LATW, page 1-6. IEEE, (2010)A compact IGBT electro-thermal model in Verilog-A for fast system-level simulation., , , , and . IECON, page 3793-3798. IEEE, (2016)An on-line fault detection technique based on embedded debug features., , , , , and . IOLTS, page 167-172. IEEE Computer Society, (2010)Software-Based Self-Test for Delay Faults., , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 1-19. Springer, (2019)A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions., , , , , and . VTS, page 389-394. IEEE Computer Society, (2008)