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Disambiguation of "Huang, Shi-Yu"

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A wide-range clock signal generation scheme for speed grading of a logic core.

, , , and . HPCS, page 125-129. IEEE, (2016)

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Yu Shi

Shi-Ming Huang

Yu-E Shi

Yu-Hwa Huang

Yu-Han Huang

 

Other publications of authors with the same name

A UWB IR timed-array radar using time-shifted direct-sampling architecture., , , , , , , , , and 3 other author(s). VLSIC, page 54-55. IEEE, (2012)Cell-based delay locked loop compiler., and . ISOCC, page 91-92. IEEE, (2016)Fault-Simulation Based Design Error Diagnosis for Sequential Circuits., , , and . DAC, page 632-637. ACM Press, (1998)On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs., , , and . ETS, page 1-2. IEEE, (2014)Towards the logic defect diagnosis for partial-scan designs.. ASP-DAC, page 313-318. ACM, (2001)Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration., and . ITC, page 1-10. IEEE, (2019)Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (12): 2240-2249 (2013)Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain., and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (8): 690-694 (2007)A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (10): 1031-1035 (2008)Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)., and . IEEE J. Solid State Circuits, 44 (2): 642-649 (2009)