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Disambiguation of "Parker, Benjamin D."

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A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.

, , , , , , , , and . CICC, page 1-4. IEEE, (2015)

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Benjamin D Hager

Benjamin D Weger

Benjamin D Gutknecht

Thomas Parker

David Parker

 

Other publications of authors with the same name

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 47 (4): 884-896 (2012)A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (12): 2633-2645 (2005)A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , and . CICC, page 1-4. IEEE, (2015)A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (8): 2009-2017 (2013)Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits., , , , , , , , and . IEEE Des. Test, 31 (6): 8-18 (2014)A High-Resolution Minimicroscope System for Wireless Real-Time Monitoring., , , , , , and . IEEE Trans. Biomed. Eng., 65 (7): 1524-1531 (2018)3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI., , , , , , , , , and 1 other author(s). ISSCC, page 56-57. IEEE, (2016)A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation., , , , , , , , , and . FPGA, page 153-162. ACM, (2012)A semi-digital delay-locked loop using an analog-based finite state machine., , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (11): 635-639 (2004)