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HELIX-UP: relaxing program semantics to unleash parallelization.

, , , and . CGO, page 235-245. IEEE Computer Society, (2015)

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Pipelined parallel architecture for high throughput MAP detectors., , and . ISCAS (2), page 505-508. IEEE, (2004)Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability., , , and . IEEE Micro, 28 (1): 60-68 (2008)Helix: Making the Extraction of Thread-Level Parallelism Mainstream., , , , and . IEEE Micro, 32 (4): 8-18 (2012)Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity., , , , , and . IEEE Micro, 30 (1): 110 (2010)A case for efficient accelerator design space exploration via Bayesian optimization., , , , , , and . ISLPED, page 1-6. IEEE, (2017)A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction., , and . CICC, page 459-462. IEEE, (2008)Digital wireline and PLL techniques., and . CICC, IEEE, (2009)Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS., , , and . CICC, page 1-4. IEEE, (2013)A binary-activation, multi-level weight RNN and training algorithm for processing-in-memory inference with eNVM., , and . CoRR, (2019)Evaluation of voltage stacking for near-threshold multicore computing., , and . ISLPED, page 373-378. ACM, (2012)