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Disambiguation of "Andersson, Oskar"

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Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS.

, , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (6): 806-817 (2016)

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Magnus Oskarsson

Paul Andersson

Gunther Andersson

Christina Andersson

Olaf Anderßon

 

Other publications of authors with the same name

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments., , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (1): 150-163 (January 2024)A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs., , , , , and . VLSI-SoC, page 380-385. IEEE, (2013)An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI., , , , and . A-SSCC, page 229-232. IEEE, (2016)Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (6): 806-817 (2016)Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS., , , , and . ESSCIRC, page 197-200. IEEE, (2013)A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks., , , and . ISCAS, page 1-5. IEEE, (2023)A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS., , , and . ESSCIRC, page 243-246. IEEE, (2014)65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography., , , and . IET Comput. Digit. Tech., 12 (2): 62-67 (2018)A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI., , , , , and . ESSCIRC, page 429-432. IEEE, (2016)Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS., , and . NORCHIP, page 1-4. IEEE, (2011)