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Disambiguation of "Torres, Andres J."

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Rapid layout pattern classification.

, , , and . ASP-DAC, page 781-786. IEEE, (2011)

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Andres Torres

Andrés Camilo Vásquez Torres

Verónica J Berdiñas Torres

Luis Torres

Törres Viland

 

Other publications of authors with the same name

Combining lithography and Directed Self Assembly for the manufacturing of vias: Connections to graph coloring problems, integer programming formulations, and numerical experiments., , , and . Eur. J. Oper. Res., 280 (2): 453-468 (2020)Overview and development of EDA tools for integration of DSA into patterning solutions., , , , , , , , and . ISQED, page 99-103. IEEE, (2017)High performance lithographic hotspot detection using hierarchically refined machine learning., , , and . ASP-DAC, page 775-780. IEEE, (2011)Rapid layout pattern classification., , , and . ASP-DAC, page 781-786. IEEE, (2011)High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (11): 1621-1634 (2011)DSA-aware multiple patterning for the manufacturing of vias: Connections to graph coloring problems, IP formulations, and numerical experiments., , , and . CoRR, (2019)Advanced multi-patterning and hybrid lithography techniques., and . ASP-DAC, page 611-616. IEEE, (2016)A Designer's Guide to Subresolution Lithography: Enabling the Impossible to Get to the 14-nm Node Tutorial., and . IEEE Des. Test, 30 (3): 70-92 (2013)The $k$-path coloring problem in graphs with bounded treewidth: an application in integrated circuit manufacturing., , , and . CoRR, (2019)The k-path coloring problem in graphs of bounded treewidth: An application in integrated circuit manufacturing., , , and . Oper. Res. Lett., 48 (5): 652-657 (2020)