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Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization.

, , and . ISCAS (1), page 477-480. IEEE, (2002)

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Timing optimization in logic with interconnect., , , and . SLIP, page 19-26. ACM, (2008)Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects., , , and . VLSI-SOC, page 99-104. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization., , and . ISCAS (1), page 477-480. IEEE, (2002)Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization., , , and . ICECS, page 125-128. IEEE, (2004)Asynchronous gate-diffusion-input (GDI) circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (8): 847-856 (2004)Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design., , , and . Integr., 47 (1): 62-70 (2014)Low-leakage repeaters for NoC interconnects., , , and . ISCAS (1), page 600-603. IEEE, (2005)An efficient implementation of D-Flip-Flop using the GDI technique., , and . ISCAS (2), page 673-676. IEEE, (2004)Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 689-696 (2010)Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (5): 566-581 (2002)