Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR., , , , , , , , and . OFC, page 1-3. IEEE, (2016)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 45 (10): 2016-2029 (2010)Session 6 overview: Ultra-high-speed wireline., , and . ISSCC, page 108-109. IEEE, (2017)A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 44 (12): 3580-3589 (2009)18-GHz Clock Distribution Using a Coupled VCO Array., , , , , and . IEICE Trans. Electron., 90-C (4): 811-822 (2007)22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS., , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 30Gb/s 2x Half-Baud-Rate CDR., , , , , and . CICC, page 1-4. IEEE, (2019)A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS., , , , , , and . CICC, page 1-4. IEEE, (2010)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)