BibSonomy publications for /author/Argyrides http://www.bibsonomy.org/author/Argyrides BibSonomy RSS Feed for /author/Argyrides Single Error Correcting Finite Field Multipliers Over GF(2m). dblp http://www.bibsonomy.org/bibtex/21e02595bb85bb39a478c50782a51be2a/dblp dblp 2008-05-16T00:00:00+02:00 dblp
Single Error Correcting Finite Field Multipliers Over GF(2m).
Jimson Mathew and Costas Argyrides and Abusaleh M. Jabir and Hafizur Rahaman and Dhiraj K. Pradhan VLSI Design 33-38 (2008)
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]]> Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. dblp http://www.bibsonomy.org/bibtex/2ecf47bfb1898cdd9742fd2390b182e7d/dblp dblp 2008-05-07T00:00:00+02:00 dblp
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
Carlos Arthur Lang Lisbôa and Costas Argyrides and Dhiraj K. Pradhan and Luigi Carro VTS 363-370 (2008)
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]]> CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. dblp http://www.bibsonomy.org/bibtex/2533de94323df0e674a59ebd434aaeede/dblp dblp 2007-07-16T00:00:00+02:00 dblp
CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs.
Hamid R. Zarandi and Seyed Ghassem Miremadi and Costas Argyrides and Dhiraj K. Pradhan ISCAS 3696-3699 (2007)
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]]> Multiple Upsets Tolerance in SRAM Memory. dblp http://www.bibsonomy.org/bibtex/29111b280e508a708d6a187986ab1d15c/dblp dblp 2007-07-16T00:00:00+02:00 dblp
Multiple Upsets Tolerance in SRAM Memory.
Costas Argyrides and Hamid R. Zarandi and Dhiraj K. Pradhan ISCAS 365-368 (2007)
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]]> Highly Reliable Power Aware Memory Design. dblp http://www.bibsonomy.org/bibtex/28fca669e0f246d9fa9e19836576e2be6/dblp dblp 2007-07-09T00:00:00+02:00 dblp
Highly Reliable Power Aware Memory Design.
Costas Argyrides and Dhiraj K. Pradhan IOLTS 189-190 (2007)
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]]> Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. dblp http://www.bibsonomy.org/bibtex/2b339f794e0aecde1ed88a4d957952db5/dblp dblp 2007-06-23T00:00:00+02:00 dblp
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.
Hamid R. Zarandi and Seyed Ghassem Miremadi and Costas Argyrides and Dhiraj K. Pradhan IPDPS 1-6 (2007)
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