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<rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" xmlns:burst="http://xmlns.com/burst/0.1/" xmlns:xsd="http://www.w3.org/2001/XMLSchema#" xmlns="http://purl.org/rss/1.0/" xmlns:admin="http://webns.net/mvcb/" xmlns:rdfs="http://www.w3.org/2000/01/rdf-schema#" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:owl="http://www.w3.org/2002/07/owl#" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:syn="http://purl.org/rss/1.0/modules/syndication/" xmlns:swrc="http://swrc.ontoware.org/ontology#" xmlns:cc="http://web.resource.org/cc/"><channel rdf:about="http://www.bibsonomy.org/author/Gronthoud"><title>BibSonomy publications for /author/Gronthoud</title><link>BibSonomypublrss/author/Gronthoud</link><description>BibSonomy RSS feed for /author/Gronthoud</description><dc:date>2012-02-16T06:33:11+01:00</dc:date><items><rdf:Seq><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/20bf26f3672d025d393a1d30076903a4e/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/223e1c34f22f75bb7a8e9f1def646b3b5/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/273c7f9ac52b7cfa936286e7577e68456/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/213cb891579f6880c5fa02fdcde170693/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/29b7d8a3b952fbddcdb326b52deeb4cfb/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/2d687b674a7bce73fd783dd0163019298/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/23bf94cc44e8a943cc56bf332d9af2f83/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/24189f6964f30f0b71de36bfa1aee13ff/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/200c75def88755e0dfbbf8e65874110d7/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/237c3a0cfa6bb80e53c094bb1310d3998/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/2b9d92d0aa91a11e1e702a4eb410fcee1/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/2b8b22b55779e62446b50ee043d779df4/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/20a399438651f48f67105d42faeb47fd8/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/2b8154d17bedbe92ff85d7ff75910b5d8/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/211aedb746d44981daf8890ea8d6512c4/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/2fcb33c235bcf91aa5aa2c516e7e03b3c/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/20531af9f0ebbc6afe00a2a1dae7c2341/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/225ad728e445693cf9b8d86bbfc32785d/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/282b33bdd3bc5214f870b238ef70fa484/dblp"/><rdf:li rdf:resource="http://www.bibsonomy.org/bibtex/2d455d63dc5670f7038417e7365901e66/dblp"/></rdf:Seq></items></channel><item rdf:about="http://www.bibsonomy.org/bibtex/20bf26f3672d025d393a1d30076903a4e/dblp"><title>Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?</title><link>http://www.bibsonomy.org/bibtex/20bf26f3672d025d393a1d30076903a4e/dblp</link><dc:creator>dblp</dc:creator><dc:date>2012-02-08T00:00:00+01:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Moore&#034;&gt;Will R. Moore&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;, &lt;a href=&#034;/author/Baker&#034;&gt;Keith Baker&lt;/a&gt;,  and &lt;a href=&#034;/author/Lousberg&#034;&gt;Maurice Lousberg&lt;/a&gt; &lt;/span&gt;&lt;em&gt;ITC, &lt;/em&gt;&lt;em&gt;page 95-104. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2000&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics></item><item rdf:about="http://www.bibsonomy.org/bibtex/223e1c34f22f75bb7a8e9f1def646b3b5/dblp"><title>Power Supply Noise in Delay Testing.</title><link>http://www.bibsonomy.org/bibtex/223e1c34f22f75bb7a8e9f1def646b3b5/dblp</link><dc:creator>dblp</dc:creator><dc:date>2012-02-08T00:00:00+01:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/0006&#034;&gt;Jing Wang 0006&lt;/a&gt;, &lt;a href=&#034;/author/Walker&#034;&gt;D. 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Majhi&lt;/a&gt;, &lt;a href=&#034;/author/Kruseman&#034;&gt;Bram Kruseman&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;, &lt;a href=&#034;/author/Villagra&#034;&gt;Luis Elvira Villagra&lt;/a&gt;, &lt;a href=&#034;/author/van de Wiel&#034;&gt;Paul van de Wiel&lt;/a&gt;,  and &lt;a href=&#034;/author/Eichenberger&#034;&gt;Stefan Eichenberger&lt;/a&gt; &lt;/span&gt;&lt;em&gt;ITC, &lt;/em&gt;&lt;em&gt;page 1-10. &lt;/em&gt;&lt;em&gt;IEEE, &lt;/em&gt;(&lt;em&gt;2006&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics></item><item rdf:about="http://www.bibsonomy.org/bibtex/273c7f9ac52b7cfa936286e7577e68456/dblp"><title>A novel stuck-at based method for transistor stuck-open fault diagnosis.</title><link>http://www.bibsonomy.org/bibtex/273c7f9ac52b7cfa936286e7577e68456/dblp</link><dc:creator>dblp</dc:creator><dc:date>2012-02-07T00:00:00+01:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Fan&#034;&gt;Xinyue Fan&lt;/a&gt;, &lt;a href=&#034;/author/Moore&#034;&gt;Will R. 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Majhi&lt;/a&gt;, &lt;a href=&#034;/author/Azimane&#034;&gt;Mohamed Azimane&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;, &lt;a href=&#034;/author/Lousberg&#034;&gt;Maurice Lousberg&lt;/a&gt;, &lt;a href=&#034;/author/Eichenberger&#034;&gt;Stefan Eichenberger&lt;/a&gt;,  and &lt;a href=&#034;/author/Bowen&#034;&gt;Fred Bowen&lt;/a&gt; &lt;/span&gt;&lt;em&gt;CoRR&lt;/em&gt;  (&lt;em&gt;2007&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics></item><item rdf:about="http://www.bibsonomy.org/bibtex/2d687b674a7bce73fd783dd0163019298/dblp"><title>Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design.</title><link>http://www.bibsonomy.org/bibtex/2d687b674a7bce73fd783dd0163019298/dblp</link><dc:creator>dblp</dc:creator><dc:date>2011-08-25T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Zivkovic&#034;&gt;Vladimir A. Zivkovic&lt;/a&gt;, &lt;a href=&#034;/author/van der Heyden&#034;&gt;Frank van der Heyden&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;,  and &lt;a href=&#034;/author/de Jong&#034;&gt;Frans de Jong&lt;/a&gt; &lt;/span&gt;&lt;em&gt;European Test Symposium, &lt;/em&gt;&lt;em&gt;page 27-32. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2008&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics></item><item rdf:about="http://www.bibsonomy.org/bibtex/23bf94cc44e8a943cc56bf332d9af2f83/dblp"><title>Extending gate-level diagnosis tools to CMOS intra-gate faults.</title><link>http://www.bibsonomy.org/bibtex/23bf94cc44e8a943cc56bf332d9af2f83/dblp</link><dc:creator>dblp</dc:creator><dc:date>2011-06-22T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Fan&#034;&gt;Xinyue Fan&lt;/a&gt;, &lt;a href=&#034;/author/Moore&#034;&gt;Will R. Moore&lt;/a&gt;, &lt;a href=&#034;/author/Hora&#034;&gt;Camelia Hora&lt;/a&gt;,  and &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt; &lt;/span&gt;&lt;em&gt;IET Computers &amp;amp; Digital Techniques&lt;/em&gt; &lt;em&gt;1(6):685-693&lt;/em&gt; (&lt;em&gt;2007&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics></item><item rdf:about="http://www.bibsonomy.org/bibtex/24189f6964f30f0b71de36bfa1aee13ff/dblp"><title>A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis.</title><link>http://www.bibsonomy.org/bibtex/24189f6964f30f0b71de36bfa1aee13ff/dblp</link><dc:creator>dblp</dc:creator><dc:date>2011-06-22T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Fan&#034;&gt;Xinyue Fan&lt;/a&gt;, &lt;a href=&#034;/author/Moore&#034;&gt;Will R. Moore&lt;/a&gt;, &lt;a href=&#034;/author/Hora&#034;&gt;Camelia Hora&lt;/a&gt;, &lt;a href=&#034;/author/Konijnenburg&#034;&gt;Mario H. Konijnenburg&lt;/a&gt;,  and &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt; &lt;/span&gt;&lt;em&gt;VTS, &lt;/em&gt;&lt;em&gt;page 266-271. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2006&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics></item><item rdf:about="http://www.bibsonomy.org/bibtex/200c75def88755e0dfbbf8e65874110d7/dblp"><title>Algorithms for ADC Multi-site Test with Digital Input Stimulus.</title><link>http://www.bibsonomy.org/bibtex/200c75def88755e0dfbbf8e65874110d7/dblp</link><dc:creator>dblp</dc:creator><dc:date>2010-08-27T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Sheng&#034;&gt;Xiaoqin Sheng&lt;/a&gt;, &lt;a href=&#034;/author/Kerkhoff&#034;&gt;Hans G. Kerkhoff&lt;/a&gt;, &lt;a href=&#034;/author/Zjajo&#034;&gt;Amir Zjajo&lt;/a&gt;,  and &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt; &lt;/span&gt;&lt;em&gt;European Test Symposium, &lt;/em&gt;&lt;em&gt;page 45-50. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2009&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics></item><item rdf:about="http://www.bibsonomy.org/bibtex/237c3a0cfa6bb80e53c094bb1310d3998/dblp"><title>Modeling Power Supply Noise in Delay Testing.</title><link>http://www.bibsonomy.org/bibtex/237c3a0cfa6bb80e53c094bb1310d3998/dblp</link><dc:creator>dblp</dc:creator><dc:date>2009-11-25T00:00:00+01:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/0006&#034;&gt;Jing Wang 0006&lt;/a&gt;, &lt;a href=&#034;/author/Walker&#034;&gt;Duncan M. Hank Walker&lt;/a&gt;, &lt;a href=&#034;/author/Lu&#034;&gt;Xiang Lu&lt;/a&gt;, &lt;a href=&#034;/author/Majhi&#034;&gt;Ananta K. Majhi&lt;/a&gt;, &lt;a href=&#034;/author/Kruseman&#034;&gt;Bram Kruseman&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;, &lt;a href=&#034;/author/Villagra&#034;&gt;Luis Elvira Villagra&lt;/a&gt;, &lt;a href=&#034;/author/van de Wiel&#034;&gt;Paul J. A. M. van de Wiel&lt;/a&gt;,  and &lt;a href=&#034;/author/Eichenberger&#034;&gt;Stefan Eichenberger&lt;/a&gt; &lt;/span&gt;&lt;em&gt;IEEE Design &amp;amp; Test of Computers&lt;/em&gt; &lt;em&gt;24(3):226-234&lt;/em&gt; (&lt;em&gt;2007&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/2b9d92d0aa91a11e1e702a4eb410fcee1/dblp"><title>Multi-VDD Testing for Analog Circuits.</title><link>http://www.bibsonomy.org/bibtex/2b9d92d0aa91a11e1e702a4eb410fcee1/dblp</link><dc:creator>dblp</dc:creator><dc:date>2007-09-18T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/de Gyvez&#034;&gt;José Pineda de Gyvez&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;,  and &lt;a href=&#034;/author/Amine&#034;&gt;Rashid Amine&lt;/a&gt; &lt;/span&gt;&lt;em&gt;J. Electronic Testing&lt;/em&gt; &lt;em&gt;21(3):311-322&lt;/em&gt; (&lt;em&gt;2005&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/2b8b22b55779e62446b50ee043d779df4/dblp"><title>Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits.</title><link>http://www.bibsonomy.org/bibtex/2b8b22b55779e62446b50ee043d779df4/dblp</link><dc:creator>dblp</dc:creator><dc:date>2007-09-18T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Zjajo&#034;&gt;Amir Zjajo&lt;/a&gt;, &lt;a href=&#034;/author/de Gyvez&#034;&gt;José Pineda de Gyvez&lt;/a&gt;,  and &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt; &lt;/span&gt;&lt;em&gt;J. Electronic Testing&lt;/em&gt; &lt;em&gt;22(4-6):399-409&lt;/em&gt; (&lt;em&gt;2006&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/20a399438651f48f67105d42faeb47fd8/dblp"><title>Re-configuration of sub-blocks for effective application of time domain tests.</title><link>http://www.bibsonomy.org/bibtex/20a399438651f48f67105d42faeb47fd8/dblp</link><dc:creator>dblp</dc:creator><dc:date>2007-06-22T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Anders&#034;&gt;Jens Anders&lt;/a&gt;, &lt;a href=&#034;/author/Krishnan&#034;&gt;Shaji Krishnan&lt;/a&gt;,  and &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt; &lt;/span&gt;&lt;em&gt;DATE, &lt;/em&gt;&lt;em&gt;page 707-712. &lt;/em&gt;&lt;em&gt;ACM, &lt;/em&gt;(&lt;em&gt;2007&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/2b8154d17bedbe92ff85d7ff75910b5d8/dblp"><title>On Performance Testing with Path Delay Patterns.</title><link>http://www.bibsonomy.org/bibtex/2b8154d17bedbe92ff85d7ff75910b5d8/dblp</link><dc:creator>dblp</dc:creator><dc:date>2007-06-04T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Kruseman&#034;&gt;Bram Kruseman&lt;/a&gt;, &lt;a href=&#034;/author/Majhi&#034;&gt;Ananta K. Majhi&lt;/a&gt;,  and &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt; &lt;/span&gt;&lt;em&gt;VTS, &lt;/em&gt;&lt;em&gt;page 29-34. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2007&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/211aedb746d44981daf8890ea8d6512c4/dblp"><title>On Hazard-free Patterns for Fine-delay Fault Testing.</title><link>http://www.bibsonomy.org/bibtex/211aedb746d44981daf8890ea8d6512c4/dblp</link><dc:creator>dblp</dc:creator><dc:date>2006-09-21T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Kruseman&#034;&gt;Bram Kruseman&lt;/a&gt;, &lt;a href=&#034;/author/Majhi&#034;&gt;Ananta K. Majhi&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;,  and &lt;a href=&#034;/author/Eichenberger&#034;&gt;Stefan Eichenberger&lt;/a&gt; &lt;/span&gt;&lt;em&gt;ITC, &lt;/em&gt;&lt;em&gt;page 213-222. &lt;/em&gt;&lt;em&gt;IEEE, &lt;/em&gt;(&lt;em&gt;2004&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/2fcb33c235bcf91aa5aa2c516e7e03b3c/dblp"><title>Power Supply Ramping for Quasi-static Testing of PLLs.</title><link>http://www.bibsonomy.org/bibtex/2fcb33c235bcf91aa5aa2c516e7e03b3c/dblp</link><dc:creator>dblp</dc:creator><dc:date>2006-09-21T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/de Gyvez&#034;&gt;José Pineda de Gyvez&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;, &lt;a href=&#034;/author/Cenci&#034;&gt;Cristiano Cenci&lt;/a&gt;, &lt;a href=&#034;/author/Posch&#034;&gt;Martin Posch&lt;/a&gt;, &lt;a href=&#034;/author/Burger&#034;&gt;Thomas Burger&lt;/a&gt;,  and &lt;a href=&#034;/author/Koller&#034;&gt;Manfred Koller&lt;/a&gt; &lt;/span&gt;&lt;em&gt;ITC, &lt;/em&gt;&lt;em&gt;page 980-987. &lt;/em&gt;&lt;em&gt;IEEE, &lt;/em&gt;(&lt;em&gt;2004&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/20531af9f0ebbc6afe00a2a1dae7c2341/dblp"><title>A New Algorithm for Dynamic Faults Detection in RAMs.</title><link>http://www.bibsonomy.org/bibtex/20531af9f0ebbc6afe00a2a1dae7c2341/dblp</link><dc:creator>dblp</dc:creator><dc:date>2006-01-23T00:00:00+01:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Azimane&#034;&gt;Mohamed Azimane&lt;/a&gt;, &lt;a href=&#034;/author/Majhi&#034;&gt;Ananta K. Majhi&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;,  and &lt;a href=&#034;/author/Lousberg&#034;&gt;Maurice Lousberg&lt;/a&gt; &lt;/span&gt;&lt;em&gt;VTS, &lt;/em&gt;&lt;em&gt;page 177-182. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2005&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/225ad728e445693cf9b8d86bbfc32785d/dblp"><title>Memory Testing Under Different Stress Conditions: An Industrial Evaluation.</title><link>http://www.bibsonomy.org/bibtex/225ad728e445693cf9b8d86bbfc32785d/dblp</link><dc:creator>dblp</dc:creator><dc:date>2005-04-13T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Majhi&#034;&gt;Ananta K. Majhi&lt;/a&gt;, &lt;a href=&#034;/author/Azimane&#034;&gt;Mohamed Azimane&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;, &lt;a href=&#034;/author/Lousberg&#034;&gt;Maurice Lousberg&lt;/a&gt;, &lt;a href=&#034;/author/Eichenberger&#034;&gt;Stefan Eichenberger&lt;/a&gt;,  and &lt;a href=&#034;/author/Bowen&#034;&gt;Fred Bowen&lt;/a&gt; &lt;/span&gt;&lt;em&gt;DATE, &lt;/em&gt;&lt;em&gt;page 438-443. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2005&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/282b33bdd3bc5214f870b238ef70fa484/dblp"><title>Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.</title><link>http://www.bibsonomy.org/bibtex/282b33bdd3bc5214f870b238ef70fa484/dblp</link><dc:creator>dblp</dc:creator><dc:date>2004-07-06T00:00:00+02:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/Majhi&#034;&gt;Ananta K. Majhi&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;, &lt;a href=&#034;/author/Hora&#034;&gt;Camelia Hora&lt;/a&gt;, &lt;a href=&#034;/author/Lousberg&#034;&gt;Maurice Lousberg&lt;/a&gt;, &lt;a href=&#034;/author/Valer&#034;&gt;Pop Valer&lt;/a&gt;,  and &lt;a href=&#034;/author/Eichenberger&#034;&gt;Stefan Eichenberger&lt;/a&gt; &lt;/span&gt;&lt;em&gt;VTS, &lt;/em&gt;&lt;em&gt;page 345-350. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2003&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item><item rdf:about="http://www.bibsonomy.org/bibtex/2d455d63dc5670f7038417e7365901e66/dblp"><title>VDD Ramp Testing for RF Circuits.</title><link>http://www.bibsonomy.org/bibtex/2d455d63dc5670f7038417e7365901e66/dblp</link><dc:creator>dblp</dc:creator><dc:date>2004-02-25T00:00:00+01:00</dc:date><dc:subject>dblp </dc:subject><content:encoded>&lt;span class=&#034;authorEditorList&#034;&gt;&lt;a href=&#034;/author/de Gyvez&#034;&gt;José Pineda de Gyvez&lt;/a&gt;, &lt;a href=&#034;/author/Gronthoud&#034;&gt;Guido Gronthoud&lt;/a&gt;,  and &lt;a href=&#034;/author/Amine&#034;&gt;Rashid Amine&lt;/a&gt; &lt;/span&gt;&lt;em&gt;ITC, &lt;/em&gt;&lt;em&gt;page 651-658. &lt;/em&gt;&lt;em&gt;IEEE Computer Society, &lt;/em&gt;(&lt;em&gt;2003&lt;/em&gt;)</content:encoded><taxo:topics><rdf:Bag><rdf:li rdf:resource="http://www.bibsonomy.org/tag/dblp"/></rdf:Bag></taxo:topics><description>dblp</description></item></rdf:RDF>
