BibSonomy publications for /author/Kriplani http://www.bibsonomy.org/author/Kriplani BibSonomy RSS Feed for /author/Kriplani Vortex phases and dynamics in high-temperature and conventional amorphous superconductors Physica A http://www.bibsonomy.org/bibtex/2833ecedf1919ad0dd3c77bbce909868d/smicha smicha 2008-04-22T10:36:30+02:00 imported
Vortex phases and dynamics in high-temperature and conventional amorphous superconductors
N. C. Yeh and W. Jiang and D. S. Reed and U. Kriplani and F. Holtzberg and M. Konczykowski and C. C. Tsuei and C. C. Chi Physica A: Statistical and Theoretical Physics 200 374--383 (1993)
to imported by smicha on 2008-04-22 10:36:30
]]> Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. dblp http://www.bibsonomy.org/bibtex/23066f271d2f672ccad786484bb32198c/dblp dblp 2006-05-30T00:00:00+02:00 dblp
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
Harish Kriplani and Farid N. Najm and Ibrahim N. Hajj IEEE Trans. on CAD of Integrated Circuits and Systems 14 998-1012 (1995)
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]]> Maximum Current Estimation in CMOS Circuits. dblp http://www.bibsonomy.org/bibtex/2cb577ff84a4fcf2146b8ac7aff1d566f/dblp dblp 2006-03-14T00:00:00+01:00 dblp
Maximum Current Estimation in CMOS Circuits.
Harish Kriplani and Farid N. Najm and Ibrahim N. Hajj DAC 2-7 (1992)
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]]> Timing model extraction of hierarchical blocks by graph reduction. dblp http://www.bibsonomy.org/bibtex/2d7eb478172b438b79e6f3e139cb85bcc/dblp dblp 2002-12-16T00:00:00+01:00 dblp
Timing model extraction of hierarchical blocks by graph reduction.
Cho W. Moon and Harish Kriplani and Krishna P. Belkhale DAC 152-157 (2002)
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]]> Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. dblp http://www.bibsonomy.org/bibtex/24677d90045f8939264b696f41839f8c2/dblp dblp 2002-12-16T00:00:00+01:00 dblp
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.
Harish Kriplani and Farid N. Najm and Ping Yang and Ibrahim N. Hajj DAC 384-388 (1993)
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]]> Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. dblp http://www.bibsonomy.org/bibtex/220948cf6333e8783cd5547737bfe2318/dblp dblp 2002-04-19T00:00:00+02:00 dblp
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.
Harish Kriplani and Farid N. Najm and Ibrahim N. Hajj ISCAS 435-438 (1994)
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