BibSonomy publications for /author/Landrault http://www.bibsonomy.org/author/Landrault BibSonomy RSS Feed for /author/Landrault Embedding of a Real Time Image Stabilization Algorithm on SoPC Platform, a Chip Multi-processor Approach. dblp http://www.bibsonomy.org/bibtex/25ca2910a610df2f38a6f4fad64fb597f/dblp dblp 2008-10-22T00:00:00+02:00 dblp
Embedding of a Real Time Image Stabilization Algorithm on SoPC Platform, a Chip Multi-processor Approach.
Jean-Pierre Dérutin and Lionel Damez and Alexis Landrault ACIVS 157-169 (2008)
to dblp by dblp on 2008-10-22 00:00:00
]]> Improving Diagnosis Resolution without Physical Information. dblp http://www.bibsonomy.org/bibtex/225c79f7c9bff15fb79475d01ee294bb1/dblp dblp 2008-02-26T00:00:00+01:00 dblp
Improving Diagnosis Resolution without Physical Information.
Alexandre Rousset and Alberto Bosio and Patrick Girard and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel DELTA 210-215 (2008)
to dblp by dblp on 2008-02-26 00:00:00
]]> Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. dblp http://www.bibsonomy.org/bibtex/26c549b97ef4157515956e3de0d1f8f44/dblp dblp 2007-11-07T00:00:00+01:00 dblp
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.
Nabil Badereddine and Patrick Girard and Serge Pravossoudovitch and Arnaud Virazel and Christian Landrault VLSI-SoC 267-281 (2005)
to dblp by dblp on 2007-11-07 00:00:00
]]> A Gated Clock Scheme for Low Power Testing of Logic Cores. dblp http://www.bibsonomy.org/bibtex/267cf0191e53b12c6d4796d8cc245bc98/dblp dblp 2007-09-18T00:00:00+02:00 dblp
A Gated Clock Scheme for Low Power Testing of Logic Cores.
Yannick Bonhomme and Patrick Girard and Loïs Guiller and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel J. Electronic Testing 22 89-99 (2006)
to dblp by dblp on 2007-09-18 00:00:00
]]> Design of Routing-Constrained Low Power Scan Chains. dblp http://www.bibsonomy.org/bibtex/2e2651de09a41072034f37a837f1b892d/dblp dblp 2007-07-27T00:00:00+02:00 dblp
Design of Routing-Constrained Low Power Scan Chains.
Yannick Bonhomme and Patrick Girard and Loïs Guiller and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel DELTA 287-294 (2004)
to dblp by dblp and 1 other person on 2007-07-27 00:00:00
]]> Test Power: a Big Issue in Large SOC Designs. dblp http://www.bibsonomy.org/bibtex/2a3df516c3dc074bb594ba94dfa4d3892/dblp dblp 2007-07-27T00:00:00+02:00 dblp
Test Power: a Big Issue in Large SOC Designs.
Yannick Bonhomme and Patrick Girard and Christian Landrault and Serge Pravossoudovitch DELTA 447-449 (2002)
to dblp by dblp on 2007-07-27 00:00:00
]]> A Gated Clock Scheme for Low Power Scan-Based BIST. dblp http://www.bibsonomy.org/bibtex/2aade4501453687b6515bfe8fe60d404e/dblp dblp 2007-07-27T00:00:00+02:00 dblp
A Gated Clock Scheme for Low Power Scan-Based BIST.
Yannick Bonhomme and Patrick Girard and Loïs Guiller and Christian Landrault and Serge Pravossoudovitch IOLTW 87-89 (2001)
to dblp by dblp on 2007-07-27 00:00:00
]]> Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. dblp http://www.bibsonomy.org/bibtex/29977707f60453ff61df60f4094d66ec3/dblp dblp 2007-07-27T00:00:00+02:00 dblp
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
Yannick Bonhomme and Patrick Girard and Loïs Guiller and Christian Landrault and Serge Pravossoudovitch ITC 488-493 (2003)
to dblp by dblp on 2007-07-27 00:00:00
]]> Design of Routing-Constrained Low Power Scan Chains. dblp http://www.bibsonomy.org/bibtex/2c89517b8c739a3989352f3978d40a45a/dblp dblp 2007-07-27T00:00:00+02:00 dblp
Design of Routing-Constrained Low Power Scan Chains.
Yannick Bonhomme and Patrick Girard and Loïs Guiller and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel DATE 62-67 (2004)
to dblp by dblp and 1 other person on 2007-07-27 00:00:00
]]> A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. dblp http://www.bibsonomy.org/bibtex/2d9c60c31f3d8623009a3c011c62ea4b2/dblp dblp 2007-07-27T00:00:00+02:00 dblp
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
Yannick Bonhomme and Patrick Girard and Loïs Guiller and Christian Landrault and Serge Pravossoudovitch Asian Test Symposium 253-258 (2001)
to dblp by dblp on 2007-07-27 00:00:00
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