%0 Journal Article %1 talegaon2014selective %A Talegaon, Samir %D 2014 %J Computer Applications: An International Journal (CAIJ) %K computer %N 1 %P 1-17 %T SELECTIVE CONTEXT BLOCKING AFTER BRANCH PERFORMANCE EVALUATION FOR IMPROVING SMT PERFORMANCE %U http://airccse.com/caij/index.html %V 1 %X Simultaneous Multi-Threading (SMT) is a tech-nique by which multiple independent threads can be simulta-neously executed and it increases the system throughput. For further improving the performance of the machine one more technique known as pipelining is implemented. Pipelining allows the SMT machine to execute more than one function in the same cycle. Pipelining optimizes several processes such as fetch, decode, dispatch, issue, execute and commit. Our focus is on the Dispatch Cycle in which instructions get Dispatched from the individual re-order buffers to the shared Issue Queue. Branch Miss-Prediction reduces the throughput of SMT machine due to the instruction flush-outs. The pipeline then has to be refilled starting from the branch instruction, after changing the branch direction. It causes a delay in the pipeline after which instructions will start to commit from that particular thread and this affects the overall system throughput adversely. Our approach is to implement a technique called as selective context blocking after context-branch evaluation. According to this technique the number of instructions a thread is allowed to dispatch is controlled, if it has a higher Branch Miss-Prediction percent-age within the past certain number of Branch Instructions. As a result of this we get an overall throughput increase of up to 4 % in the performance when compared to the default algorithm.

@article{talegaon2014selective, abstract = {Simultaneous Multi-Threading (SMT) is a tech-nique by which multiple independent threads can be simulta-neously executed and it increases the system throughput. For further improving the performance of the machine one more technique known as pipelining is implemented. Pipelining allows the SMT machine to execute more than one function in the same cycle. Pipelining optimizes several processes such as fetch, decode, dispatch, issue, execute and commit. Our focus is on the Dispatch Cycle in which instructions get Dispatched from the individual re-order buffers to the shared Issue Queue. Branch Miss-Prediction reduces the throughput of SMT machine due to the instruction flush-outs. The pipeline then has to be refilled starting from the branch instruction, after changing the branch direction. It causes a delay in the pipeline after which instructions will start to commit from that particular thread and this affects the overall system throughput adversely. Our approach is to implement a technique called as selective context blocking after context-branch evaluation. According to this technique the number of instructions a thread is allowed to dispatch is controlled, if it has a higher Branch Miss-Prediction percent-age within the past certain number of Branch Instructions. As a result of this we get an overall throughput increase of up to 4 % in the performance when compared to the default algorithm. }, added-at = {2018-03-27T06:01:44.000+0200}, author = {Talegaon, Samir}, biburl = {https://www.bibsonomy.org/bibtex/2056cbfcfc859c7767c752e65ed540ba1/caij}, interhash = {0067c23d783917dc98809bca1f735be5}, intrahash = {056cbfcfc859c7767c752e65ed540ba1}, journal = {Computer Applications: An International Journal (CAIJ)}, keywords = {computer}, month = {August}, number = 1, pages = {1-17}, timestamp = {2018-03-27T06:01:44.000+0200}, title = {SELECTIVE CONTEXT BLOCKING AFTER BRANCH PERFORMANCE EVALUATION FOR IMPROVING SMT PERFORMANCE}, url = {http://airccse.com/caij/index.html}, volume = 1, year = 2014 }