%0 Conference Paper %1 conf/socc/WangCNWP16 %A Wang, Luhao %A Cui, Tiansong %A Nazarian, Shahin %A Wang, Yanzhi %A Pedram, Massoud %B SoCC %D 2016 %E Bhatia, Karan S. %E Alioto, Massimo %E Zhao, Danella %E Marshall, Andrew %E Sridhar, Ramalingam %I IEEE %K dblp %P 253-258 %T Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors. %U http://dblp.uni-trier.de/db/conf/socc/socc2016.html#WangCNWP16 %@ 978-1-5090-1367-8

@inproceedings{conf/socc/WangCNWP16, added-at = {2017-04-26T00:00:00.000+0200}, author = {Wang, Luhao and Cui, Tiansong and Nazarian, Shahin and Wang, Yanzhi and Pedram, Massoud}, biburl = {https://www.bibsonomy.org/bibtex/21669196ff2ae1379ce7d33f3b46a0ec5/dblp}, booktitle = {SoCC}, crossref = {conf/socc/2016}, editor = {Bhatia, Karan S. and Alioto, Massimo and Zhao, Danella and Marshall, Andrew and Sridhar, Ramalingam}, ee = {http://dx.doi.org/10.1109/SOCC.2016.7905480}, interhash = {015475b416c7979522443bef46ffe3f9}, intrahash = {1669196ff2ae1379ce7d33f3b46a0ec5}, isbn = {978-1-5090-1367-8}, keywords = {dblp}, pages = {253-258}, publisher = {IEEE}, timestamp = {2017-04-27T11:36:35.000+0200}, title = {Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors.}, url = {http://dblp.uni-trier.de/db/conf/socc/socc2016.html#WangCNWP16}, year = 2016 }