%0 Conference Paper %1 6209274 %A Schoeberl, M. %A Brandner, F. %A Sparsø, J. %A Kasapaki, E. %B Networks on Chip (NoCS), 2012 Sixth IEEE/ACM International Symposium on %D 2012 %K backtracking fmea noc pipeline wave %P 152-160 %R 10.1109/NOCS.2012.25 %T A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems %U http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6209274 %X This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits - all with the same bandwidth - between all nodes. This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented. The static schedule makes the NoC time-predictable and enables worst-case execution time analysis of communicating real-time tasks.

@inproceedings{6209274, abstract = {This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits - all with the same bandwidth - between all nodes. This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented. The static schedule makes the NoC time-predictable and enables worst-case execution time analysis of communicating real-time tasks.}, added-at = {2013-04-04T16:14:18.000+0200}, author = {Schoeberl, M. and Brandner, F. and Sparsø, J. and Kasapaki, E.}, biburl = {https://www.bibsonomy.org/bibtex/25ed24c8c78254eb07335a3d9a4117d66/eberle18}, booktitle = {Networks on Chip (NoCS), 2012 Sixth IEEE/ACM International Symposium on}, description = {IEEE Xplore - A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems}, doi = {10.1109/NOCS.2012.25}, interhash = {0df9c756bdc4ae9c7f5103a33b275d8f}, intrahash = {5ed24c8c78254eb07335a3d9a4117d66}, keywords = {backtracking fmea noc pipeline wave}, pages = {152-160}, timestamp = {2013-04-04T16:14:18.000+0200}, title = {A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6209274}, year = 2012 }