%0 Journal Article %1 journals/tvlsi/NiWLW21 %A Ni, Meng %A Wang, Xiao %A Li, Fule %A Wang, Zhihua %D 2021 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 7 %P 1416-1427 %T A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#NiWLW21 %V 29

@article{journals/tvlsi/NiWLW21, added-at = {2021-09-16T00:00:00.000+0200}, author = {Ni, Meng and Wang, Xiao and Li, Fule and Wang, Zhihua}, biburl = {https://www.bibsonomy.org/bibtex/2f8f4ce8e7fe67bd31c20a97f469f1096/dblp}, ee = {https://doi.org/10.1109/TVLSI.2021.3078689}, interhash = {26a601304b84d4c51cb711ca5501f54f}, intrahash = {f8f4ce8e7fe67bd31c20a97f469f1096}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 7, pages = {1416-1427}, timestamp = {2024-04-08T14:32:48.000+0200}, title = {A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#NiWLW21}, volume = 29, year = 2021 }